In general, a channel coding such as a turbo coding is used to increase the transmission efficiency of data in a communication system.
FIG. 1 is a block diagram illustrating a construction of a conventional turbo encoder. Referring to FIG. 1, the conventional turbo encoder 100 includes an internal interleaver 110 and two 8-state element encoders 120 and 130.
The conventional turbo encoder 100 performs a channel coding by using a Parallel Concatenated Convolutional Code (PCCC).
A transfer function of the 8-state element encoders 120 and 130 is defined as follows.G(D)=[1,g1(D)/g0(D)]g0(D)=1+D2+D3,g1(D)=1+D+D3 
Initial values of shift registers used in the 8-state element encoders 120 and 130 are all 0. Outputs of the conventional turbo encoder 100 are as follows.dk(0)=xk,dk(1)=zk,dk(2)=z′k,k=0,1,2, . . . ,(K−1) 
When a code block, which should be encoded, is a 0th code block, if the number of filler bits, which should be inserted, is larger than 0 (that is, F>0), inputs of the conventional turbo encoder 100 are Ck=0, k=0, . . . , (F−1) and outputs aredk(0)=<Null>,k=0, . . . ,(F−1),dk(1)=<Null>,k=0, . . . ,(F−1) An input bitstream of the conventional turbo encoder 100 is represented as C0, C1, C2, C3, . . . Ck−1 and output bitstreams of first and second 8-state element encoders 120 and 130 are represented as z0, z1, z2, z3, . . . zk−1 and z′0, z′1, z′2, z′3, . . . z′k−1, respectively. Outputs of the internal interleaver 110 of the turbo encoder are represented as C′1, C′2, . . . C′k−1, and C′0, C′1, C′2, . . . C′k−1 become inputs of the second 8-state element encoder 130.
When the inputs of the internal interleaver 110 of the conventional turbo encoder 100 are C0, C1, C2, . . . Ck−1 and the outputs of the internal interleaver 110 of the conventional turbo encoder 100 are C′0, C′1, C′2, . . . C′k−1, the relation between the input and the output is as follows.C′i=CΠ(i),i=0,1, . . . ,(K−1) 
In the above equation, an index of the input bistream and an index of the output bitstream are calculated as defined in the below equation.Π(i)=(f1*i+f2*i2)modK 
A trellis termination is performed by taking three shift register values indicating the state after all input bitstreams have been encoded as a final input bit. The final input bit is added to the back of the output bitstream after the input bitstreams have been fully encoded.
First three final bits should be used when the first 8-state element encoder 120 is terminated in a state where an operation of the second 8-state element encoder 130 is stopped. That is, a switch included in the first 8-state element encoder 120 is connected to a lower side.
Last three final bits should be used when the second 8-state element encoder 130 is terminated in a state where an operation of the first 8-state element encoder 120 is stopped. That is, a switch included in the second 8-state element encoder 130 is connected to a lower side.
Trellis termination bitstreams added to outputs are as follows.dk(0)=xk,dk+1(0)=zk+1,dk+2(0)=x′k,dk+3(0)=z′k+1 dk(1)=zk,dk+1(1)=xk+2,kk+2(1)=z′k,dk+3(1)=x′k+2 dk(2)=xk+1,dk+1(2)=zk+2,dk+2(2)=x′k+1,dk+3(2)=z′k+3 
The number of sizes (K) of input bitstreams, which can be encoded at one time, is a total of 188, and K can have values shown in the below table.
TABLE 1iKi140248356464572680788896910410112111201212813136141441515216160171681817619184201922120022208232162422425232262402724828256292643027231280322883329634304353123632037328383363934440352413604236843376443844539246400474084841649424504325144052448534565446455472564805748858496595046051261528625446356064576655926660867624686406965670672716887270473720747367575276768777847880079816808328184882864838808489685912869288794488960899769099291100892102493105694108895112096115297118498121699124810012801011312102134410313761041408105144010614721071504108153610915681101600111163211216641131696114172811517601161792117182411818561191888120192012119521221984123201612420481252112126217612722401282304129236813024321312496132256013326241342688135275213628161372880138294413930081403072141313614232001433264144332814533921463456147352014835841493648150371215137761523840153390415439681554032156409615741601584224159428816043521614416162448016345441644608165467216647361674800168486416949281704992171505617251201735184174524817553121765376177544017855041795568180563218156961825760183582418458881855952186601618760801886144
A maximum size (K) of the code block is 6144 bits. In this case, the time spent for generating an output bitstream by encoding an input bitstream corresponds to a 6144+3+3 clock cycle in the implementation of hardware. When the time is calculated based on a basic sampling frequency (30.72 MHz) in LTE or LTE-Advanced, the time of about 200.2 us is required and the time corresponds to one subframe of about 20%.
Further, three code blocks, which are outputs of the conventional turbo encoder 100, should be converted to a structure body in the unit of 32 bits before entering a rate matching, which is a next signal processing step, and insufficient bits are filled with null bit.
However, the conventional turbo encoder 100 takes a long time for encoding since the conventional turbo encoder 100 performs the encoding in the unit of bits.